A typical magnetic tunnel junction (MTJ) memory device includes an array of memory cells. Each of the cells may be constructed of two layers of magnetic film, separated by a dielectric layer. The magnetization of one of the layers is alterable and the magnetization of the other layer is fixed or “pinned” in a particular direction. The magnetic film layer having alterable magnetization may be referred to as a “data storage layer” and the magnetic film layer which is pinned may be referred to as a “reference layer.”
FIG. 1 is a plan view illustration of a simplified magnetic random access memory (MRAM) array, which is an exemplar MTJ memory device. The array 100 includes memory cells 120, row lines 130, and column lines 132. The row lines 130 and column-lines 132 are herein referred to collectively as “write lines,” and they may also be used to read data stored in the data storage layer. The memory cells 120 are positioned at each intersection of a row line 130 and a column line 132. Generally, the row lines 130 and column lines 132 are arranged in orthogonal relation to one another and the memory cells 120 are positioned between the column lines 132 and the row lines 130.
FIGS. 2A, 2B and 2C collectively illustrate the storage of a bit of data in a single memory cell 120 of the MRAM array of FIG. 1. As illustrated in FIG. 2A, memory cell 120 includes an active magnetic data film 122 and a pinned magnetic film 124 which are separated by a dielectric region 126. The orientation of magnetization in the active magnetic data film 122 is not fixed and can assume either of two stable orientations, as shown by arrow M1. In contrast, the pinned magnetic film 124 has a fixed orientation of magnetization, as shown by arrow M2. The active magnetic data film 122 rotates its orientation of magnetization in response to electrical currents applied to the write lines (i.e., the column lines 130 and write lines 132 of FIG. 1) during a write operation to the memory cell 120. The first logic state of the data bit stored in memory cell 120 is indicated when M1 and M2 are parallel to each other, as illustrated in FIG. 2C. When M1 and M2 are parallel, a logic “1” state may be said to be stored in the memory cell 120. Conversely, a second logic state is indicated when M1 and M2 are anti-parallel to each other, as illustrated in FIG. 2B. When M1 and M2 are anti-parallel, a logic “0” state may be said to be stored in the memory cell 120. In FIGS. 2B and 2C, the dielectric region 126 has been omitted. Although FIGS. 2A, 2B and 2C collectively illustrate the active magnetic data film 122 positioned above the pinned magnetic film 124, the pinned magnetic film 124 alternatively may be positioned above the active magnetic data film 122.
When measured by a current flowing parallel to axle 123, the resistance of the memory cell 120 differs according to the relative orientations of M1 and M2. When M1 and M2 are anti-parallel (e.g., the logic “0” state), the resistance of the memory cell 120 is at its highest. On the other hand, the resistance of the memory cell 120 is at its lowest when the orientations of M1 and M2 are parallel (e.g., the logic “1” state). Consequently, the logic state of the data bit stored in the memory cell 120 can be determined by measuring, either directly or indirectly, the resistance of the memory cell 120.
A selected magnetic memory cell 120 may be given a desired logic state by applying electrical currents to the particular row and column lines that intersect at the selected magnetic memory cell. An electrical current applied to the particular column line may generate a magnetic field substantially aligned along the easy axis of the selected magnetic memory cell. The magnetic field aligned to the easy axis is generally referred to as a longitudinal write field. An electrical current applied to the particular row line may generate a magnetic field substantially perpendicular to the easy axis of the selected magnetic memory cell. Generally, only one selected magnetic memory cell receives both the longitudinal and the perpendicular write fields at any one time. Non-selected memory cells that are coupled to the same row line as the selected cell receive only the perpendicular write field. Non-selected memory cells that are coupled to the same column line as the selected cell receive only the longitudinal write field.
Because MTJ memory devices operate on the principle of the quantum mechanical tunnel effect, the magnitude of the sense current in a particular cell, and hence the resistance of the cell, is very highly dependent on the thickness of the dielectric layer 126. Because variations in dielectric thickness within an array of MTJ devices cannot be completely eliminated by existing thin film process techniques, these variations can cause seemingly disproportionate variations in the magnitude of the sense current that is measured within different cells in the array. These variations can lead to ambiguity in determining the logic state of different cells within an array. The practical implications of this ambiguity are such that, when operating an MTJ memory device array, a large number of errors potentially may occur during the process of retrieving data if the data state of any one cell is determined by comparing that cell's resistance to some pre-determined threshold value. This ambiguity occurs because the difference in resistance between cells having the same stored logic state can easily exceed the difference in resistance of one cell as its logic state is switched from a “1” to a “0”.
One way to overcome this ambiguity is to employ a data retrieval process known as a destructive read. A destructive read generally involves the following steps: (1) measuring the magnitude of sense current in a cell a first time in response to an applied voltage; (2) writing the cell to a known (previously determined) state (i.e., to a “1” or a “0”); (3) measuring the magnitude of the sense current in the cell a second time in response to a second application of the same applied voltage previously applied in step 1; and (4) determining whether the logic state of the bit in question was originally a “1” or a “0” based on the difference of the magnitude of the sense current between the first measurement and the second measurement. In addition, if the original state of the cell, as determined in step 4, is different from the state to which the cell was written during step 2, the cell must be returned to its original state by another write operation. For example, if the cell was written to a “11” during step 2, and the determination in step 4 indicated that the cell was originally a “0”, the cell must be written back to its original “0” state after the destructive read is completed. On the other hand, if the cell was written to a “1” during step 2, and the determination in step 4 indicated that the cell was originally a “1”, it would be not be necessary to perform a re-write operation to return the cell to its original state.
Although a destructive read process can be used to determine the state of a cell, this process has several shortcomings. Because the destructive read process requires that the cell be written to a known value and then, in some cases, written back to its original value, the destructive read process markedly increases read access time. The additional write operations also increase power consumption and may decrease the life expectancy of the cell.
The destructive read process also tends to exacerbate an undesirable condition known as half-select switching. Half-select switching may occur in an MTJ memory array having N×M cells, where N and M are greater than 1, when a write operation directed at one cell inadvertently causes an undesired change of state in another cell in the array. Ideally, a cell in an MTJ memory array will switch its logic state only when subjected to both longitudinal and perpendicular write fields, and will not switch its logic state when subjected only to either the longitudinal write field or the perpendicular write field, but not both. Thus, the magnitudes of the longitudinal and the perpendicular write fields should be sufficiently high so that the cells in the array switch their logic states only when subjected to both the longitudinal write field and the perpendicular write field. At the same time, the magnitudes of the longitudinal and the perpendicular write fields should be sufficiently low so that the cells in the array do not switch their logic states when subjected only to either the longitudinal write field or the perpendicular write field, but not both. However, in some cases a cell in the array may change its state even though it is only subjected to either the longitudinal write field or the perpendicular write field, but not both. This undesirable switching of a magnetic memory cell that receives only the longitudinal or the perpendicular write field is commonly referred to as half-select switching.
Half-select switching can, if present, cause catastrophic errors when operating an MTJ memory array. For example, an attempt to switch the logic state of a first cell in an array from “0” to “1” may have the inadvertent and undesired effect of erroneously changing the logic state of a second cell in the array from “0” to “1” as well. To minimize the potential for half-select switching, it is preferable to keep the number of write operations to a minimum. However, the destructive read process requires at least one extra write operation for each cell being read, and potentially two extra write operations if the cell must be re-written to its original state. Therefore, the destructive read process increases the likelihood that half-select switching will occur.
While the invention is susceptible to various modifications and alternative forms, specific embodiments thereof are shown by way of example in the drawings and will herein be described in detail. It should be understood, however, that the drawings and detailed description thereto are not intended to limit the invention to the particular form disclosed, but on the contrary, the intention is to cover all modifications, equivalents, and alternatives falling within the spirit and scope of the present invention as defined by the appended claims.